Simulation Model Provisioning

flowchart TB
    subgraph Input_Sources["INPUT SOURCES"]
        direction TB
        A1["MATLAB/Simulink Gesamtmodell
(.mdl, .m, .mat, .yaml/.json)"]
        A2["NIP-Release Bus Descriptions
(ARXML, LDF, AUTOSAR 4.3.0)"]
        A3["Virtual ECUs
(Level 1-3 vECUs)"]
        A4["Test Bench Configuration
(YAML: HiL/Hybrid/SiL)"]
    end

    subgraph Model_Generation["MODEL GENERATION PIPELINE"]
        direction TB
        B1["Input Validation & Parsing"]
        B2["Bus Simulation Configuration"]
        B3["vECU Integration"]
        B4["Restbus Model Assembly"]
        B5["Real-Time Target Compilation"]
    end

    subgraph Quality_Gate["QUALITY GATE"]
        direction TB
        C1["DUT Error State Check"]
        C2["Virtual Vehicle Drivability Test"]
        C3["Timing & Performance Validation"]
        C4["Protocol Conformance Check"]
    end

    subgraph Deployment["DEPLOYMENT"]
        direction TB
        D1["Test Bench 1
(HiL)"]
        D2["Test Bench 2
(Hybrid HiL)"]
        D3["Test Bench 3
(SiL)"]
        D4["Model Repository
(Git/Artifactory)"]
    end

    A1 --> B1
    A2 --> B1
    A3 --> B1
    A4 --> B1
    B1 --> B2
    B2 --> B3
    B3 --> B4
    B4 --> B5
    B5 --> C1
    C1 --> C2
    C2 --> C3
    C3 --> C4
    C4 --> D1
    C4 --> D2
    C4 --> D3
    C4 --> D4

    style Input_Sources fill:#e3f2fd,stroke:#1565c0,stroke-width:2px
    style Model_Generation fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    style Quality_Gate fill:#fff3e0,stroke:#ef6c00,stroke-width:2px
    style Deployment fill:#fce4ec,stroke:#c2185b,stroke-width:2px
    

flowchart LR
    subgraph VPF_Repository["VPF Repository
(Git/Artifactory)"]
        direction TB
        M1["MATLAB/Simulink Gesamtmodell"]
        M2["SimECU Libraries
(S1, S2, S3...)"]
        M3["Physics Models
(P1, P2, P3)"]
        M4["vECU Adapter"]
    end

    subgraph NIP_Repository["NIP Repository
(Bus Descriptions)"]
        direction TB
        N1["ARXML System-Extract"]
        N2["ARXML Bus-Extract"]
        N3["ARXML ECU-Extract"]
        N4["LDF Files"]
        N5["SOME/IP Service Specs"]
    end

    subgraph vECU_Registry["vECU Registry"]
        direction TB
        V1["Level 1 vECU"]
        V2["Level 2 vECU"]
        V3["Level 3 vECU"]
    end

    subgraph TestBench_Config["Test Bench Configuration"]
        direction TB
        T1["Bench Type Definition"]
        T2["HW Configuration"]
        T3["DUT Mapping"]
        T4["Restbus Settings"]
    end

    subgraph Model_Generator["Model Generation Engine"]
        direction TB
        G1["Input Aggregator"]
        G2["Dependency Resolver"]
        G3["Configuration Manager"]
        G4["Build Orchestrator"]
    end

    M1 --> G1
    M2 --> G1
    M3 --> G1
    M4 --> G1
    N1 --> G2
    N2 --> G2
    N3 --> G2
    N4 --> G2
    N5 --> G2
    V1 --> G3
    V2 --> G3
    V3 --> G3
    T1 --> G4
    T2 --> G4
    T3 --> G4
    T4 --> G4

    G1 --> Build["Simulation Model Build"]
    G2 --> Build
    G3 --> Build
    G4 --> Build

    style VPF_Repository fill:#e3f2fd,stroke:#1565c0,stroke-width:2px
    style NIP_Repository fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    style vECU_Registry fill:#fff3e0,stroke:#ef6c00,stroke-width:2px
    style TestBench_Config fill:#fce4ec,stroke:#c2185b,stroke-width:2px
    style Model_Generator fill:#f3e5f5,stroke:#7b1fa2,stroke-width:2px
    

flowchart TB
    subgraph Validation["Input Validation Pipeline"]
        directionTB
        V1["Schema Validation
(Format Check)"]
        V2["Version Compatibility
(Tool Versions)"]
        V3["Dependency Check
(Required Artifacts)"]
        V4["Content Integrity
(Checksum/Hash)"]
        V5["Semantic Validation
(Business Rules)"]
    end

    subgraph Preprocessing["Preprocessing Stage"]
        directionTB
        P1["Format Normalization"]
        P2["Path Resolution"]
        P3["Variable Substitution"]
        P4["Configuration Merge"]
    end

    V1 --> V2
    V2 --> V3
    V3 --> V4
    V4 --> V5
    V5 --> P1
    P1 --> P2
    P2 --> P3
    P3 --> P4

    style Validation fill:#ffebee,stroke:#c62828,stroke-width:2px
    style Preprocessing fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    

flowchart TB
    subgraph Generation["Model Generation Process"]
        directionTB
        G1["Bus Simulation Assembly"]
        G2["vECU Integration"]
        G3["Physics Model Connection"]
        G4["I/O Configuration"]
        G5["Real-Time Compilation"]
    end

    subgraph Outputs["Output Artifacts"]
        directionTB
        O1["XIL Real-Time Application
(Simulation Model)"]
        O2["Parameter Datasets
(.mat, .yaml)"]
        O3["Metadata YAML
(Machine-readable)"]
        O4["Measurement Layouts
(Project Files)"]
        O5["Variable Mapping Tables"]
    end

    subgraph Delivery["Delivery Channels"]
        directionTB
        D1["Direct Deploy to
Test Benches"]
        D2["Model Repository
(Git/Artifactory)"]
        D3["Build Artifact
Storage"]
    end

    G1 --> O1
    G2 --> O1
    G3 --> O1
    G4 --> O1
    G5 --> O1

    O1 --> D1
    O2 --> D2
    O3 --> D2
    O4 --> D1
    O5 --> D2

    G1 -.-> O2
    G2 -.-> O3
    G3 -.-> O4
    G4 -.-> O5

    style Generation fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    style Outputs fill:#e3f2fd,stroke:#1565c0,stroke-width:2px
    style Delivery fill:#fff3e0,stroke:#ef6c00,stroke-width:2px
    

flowchart TB
    subgraph Central["Build Server / CI/CD"]
        CI["Pipeline Controller"]
        BUILD["Build Artifacts"]
    end

    subgraph Repository["Model Repository"]
        REPO1["Git Tags"]
        REPO2["Build Artifacts"]
        REPO3["Metadata Store"]
    end

    subgraph Benches["Test Bench Infrastructure"]
        B1["HiL Bench 1"]
        B2["HiL Bench 2"]
        B3["Hybrid HiL"]
        B4["SiL Station"]
    end

    CI --> BUILD
    BUILD --> REPO2
    BUILD --> REPO1
    CI --> REPO3

    REPO2 --> B1
    REPO2 --> B2
    REPO2 --> B3
    REPO2 --> B4

    B1 -.-> "Auto-Load" -.-> CI
    B2 -.-> "Auto-Load" -.-> CI
    B3 -.-> "Auto-Load" -.-> CI
    B4 -.-> "Auto-Load" -.-> CI

    style Central fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    style Repository fill:#e3f2fd,stroke:#1565c0,stroke-width:2px
    style Benches fill:#fce4ec,stroke:#c2185b,stroke-width:2px
    

flowchart TB
    subgraph Application["Application Layer"]
        directionTB
        APP1["Diagnostic Services"]
        APP2["Measurement & Calibration"]
        APP3["Application Software"]
    end

    subgraph Service["Service Layer"]
        directionTB
        SVC1["SOME/IP Services"]
        SVC2["BAP Protocol"]
        SVC3["VWG-SOK"]
    end

    subgraph Transport["Transport Layer"]
        directionTB
        T1["TCP/UDP"]
        T2["TLS/dTLS"]
        T3["PS15"]
    end

    subgraph Network["Network Layer"]
        directionTB
        N1["IPv4/IPv6"]
        N2["AutoSAR PDU"]
    end

    subgraph Bus["Bus Abstraction Layer"]
        directionTB
        B1["CAN(-FD)"]
        B2["LIN"]
        B3["FlexRay"]
        B4["Ethernet"]
    end

    subgraph Physical["Physical Layer"]
        directionTB
        P1["CAN Transceiver"]
        P2["LIN Transceiver"]
        P3["FlexRay Transceiver"]
        P4["ETH PHY"]
    end

    APP1 --> SVC1
    APP2 --> SVC2
    APP3 --> SVC3
    SVC1 --> T1
    SVC2 --> T2
    SVC3 --> T3
    T1 --> N1
    T2 --> N1
    T3 --> N2
    N1 --> B4
    N2 --> B1
    B1 --> P1
    B2 --> P2
    B3 --> P3
    B4 --> P4

    style Application fill:#e8f5e9,stroke:#2e7d32
    style Service fill:#fff3e0,stroke:#ef6c00
    style Transport fill:#e3f2fd,stroke:#1565c0
    style Network fill:#fce4ec,stroke:#c2185b
    style Bus fill:#f3e5f5,stroke:#7b1fa2
    style Physical fill:#efebe9,stroke:#5d4037
    

flowchart LR
    subgraph Core["Core Simulation"]
        C1["Restbus Simulation"]
        C2["Bus Protocols
(CAN/LIN/FR/ETH)"]
        C3["vECU Integration"]
    end

    subgraph Extensions["VWG Extensions"]
        directionTB
        E1["VWG-SOK
(Secure Communication)"]
        E2["TLS/dTLS
(Encrypted Channels)"]
        E3["BAP Protocol
(HMI Communication)"]
        E4["PS15 Protocol
(VW Diagnostics)"]
        E5["ViWi Interface
(Infotainment)"]
    end

    subgraph Routing["Signal Routing"]
        directionTB
        R1["ETH ↔ ETH"]
        R2["ETH ↔ FR"]
        R3["ETH ↔ CAN"]
        R4["CAN ↔ FR"]
    end

    subgraph Integration["Integration Points"]
        directionTB
        I1["ASM Interface"]
        I2["FEP Coupling"]
        I3["FPGA Interfaces"]
    end

    Core --> Extensions
    Core --> Routing
    Routing --> Integration

    style Core fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    style Extensions fill:#fff3e0,stroke:#ef6c00,stroke-width:2px
    style Routing fill:#e3f2fd,stroke:#1565c0,stroke-width:2px
    style Integration fill:#fce4ec,stroke:#c2185b,stroke-width:2px
    

flowchart TB
    subgraph Trigger["Pipeline Trigger"]
        directionTB
        T1["Input Change Event
(Webhook)"]
        T2["Scheduled Trigger
(Cron)"]
        T3["Manual Trigger
(API)"]
    end

    subgraph Artifacts["Input Artifacts"]
        A1["MATLAB/Simulink
Gesamtmodell"]
        A2["NIP Release
(Bus Descriptions)"]
        A3["vECU
Packages"]
        A4["HW Config
(YAML)"]
    end

    subgraph Build["Build Stage"]
        directionTB
        B1["Source Checkout"]
        B2["Dependency Resolution"]
        B3["Model Compilation"]
        B4["Artifact Packaging"]
    end

    subgraph Quality["Quality Gate"]
        directionTB
        Q1["DUT State Check"]
        Q2["Drivability Test"]
        Q3["Timing Validation"]
        Q4["Protocol Check"]
    end

    subgraph Deploy["Deploy Stage"]
        directionTB
        D1["Repository Upload"]
        D2["Test Bench Select"]
        D3["Model Loading"]
        D4["Bench Ready State"]
    end

    T1 --> Build
    A1 --> B1
    A2 --> B1
    A3 --> B1
    A4 --> B1
    B1 --> B2
    B2 --> B3
    B3 --> B4
    B4 --> Q1
    Q1 --> Q2
    Q2 --> Q3
    Q3 --> Q4
    Q4 --> D1
    D1 --> D2
    D2 --> D3
    D3 --> D4

    style Trigger fill:#fff3e0,stroke:#ef6c00,stroke-width:2px
    style Artifacts fill:#e3f2fd,stroke:#1565c0,stroke-width:2px
    style Build fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    style Quality fill:#ffebee,stroke:#c62828,stroke-width:2px
    style Deploy fill:#fce4ec,stroke:#c2185b,stroke-width:2px
    

flowchart TB
    START(["Build Complete"]) --> Q1

    subgraph Q1["Quality Gate 1: DUT State"]
        D1["Check DUT error-free state"]
        D1 --> D1R{Result}
    end

    D1R -->|PASS| Q2
    D1R -->|FAIL| FAIL1["Log Failure
Notify Team
Block Deployment"]

    subgraph Q2["Quality Gate 2: Drivability"]
        D2["Verify virtual vehicle
is drivable"]
        D2 --> D2R{Result}
    end

    D2R -->|PASS| Q3
    D2R -->|FAIL| FAIL2["Log Failure
Notify Team
Block Deployment"]

    subgraph Q3["Quality Gate 3: Timing"]
        D3["Validate real-time
performance"]
        D3 --> D3R{Result}
    end

    D3R -->|PASS| Q4
    D3R -->|FAIL| FAIL3["Log Failure
Notify Team
Block Deployment"]

    subgraph Q4["Quality Gate 4: Protocol"]
        D4["Check protocol
conformance"]
        D4 --> D4R{Result}
    end

    D4R -->|PASS| SUCCESS(["Deploy to
Test Bench"])
    D4R -->|FAIL| FAIL4["Log Failure
Notify Team
Block Deployment"]

    style FAIL1 fill:#ffcdd2,stroke:#c62828
    style FAIL2 fill:#ffcdd2,stroke:#c62828
    style FAIL3 fill:#ffcdd2,stroke:#c62828
    style FAIL4 fill:#ffcdd2,stroke:#c62828
    style SUCCESS fill:#c8e6c9,stroke:#2e7d32
    

flowchart TB
    subgraph Tools["Required Tools"]
        T1["VPFBasis Tool
(from SVN)"]
        T2["Model-Generator
(from GitHub)"]
    end

    subgraph Standards["Standards"]
        S1["AUTOSAR 4.3.0
(Mandatory)"]
        S2["VWG AUTOSAR Dialect
(Accepted)"]
    end

    subgraph Models["Model Components"]
        M1["MATLAB/Simulink
Gesamtmodell"]
        M2["NIP Bus
Descriptions"]
        M3["vECU
Packages"]
    end

    subgraph Outputs["Outputs"]
        O1["Simulation Model
with Version ID"]
        O2["Metadata YAML
(Dependency记录)"]
    end

    T1 --> M1
    T2 --> M1
    S1 --> M2
    S2 -.-> M2
    M1 --> O1
    M2 --> O1
    M3 --> O1
    O1 --> O2

    style Tools fill:#fff3e0,stroke:#ef6c00,stroke-width:2px
    style Standards fill:#e3f2fd,stroke:#1565c0,stroke-width:2px
    style Models fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    style Outputs fill:#fce4ec,stroke:#c2185b,stroke-width:2px
    

flowchart TB
    subgraph Simulation_Model["Simulation Model Environment"]
        directionTB
        SM["MATLAB/Simulink
Gesamtmodell"]
        BUS["Bus Simulation
(CAN/LIN/FR/ETH)"]
        SWITCH["Dynamic
Switch"]
    end

    subgraph Modes["ECU Operating Modes"]
        directionTB
        SIM["Simulated ECU
(In-Model)"]
        REAL["Real ECU
(HiL)"]
        VECU["vECU
(Hybrid HiL)"]
    end

    subgraph Connections["Signal Connections"]
        C1["I/O Signals"]
        C2["Bus Traffic"]
        C3["Control Signals"]
    end

    SM --> BUS
    BUS --> SWITCH
    SWITCH --> SIM
    SWITCH --> REAL
    SWITCH --> VECU

    SIM --> C1
    REAL --> C2
    VECU --> C3

    SIM -.->|"Closed Loop"| SM
    REAL -.->|"Closed Loop"| SM
    VECU -.->|"Closed Loop"| SM

    style Simulation_Model fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    style Modes fill:#e3f2fd,stroke:#1565c0,stroke-width:2px
    style Connections fill:#fff3e0,stroke:#ef6c00,stroke-width:2px
    

flowchart TB
    START(["Project Initiation"]) --> R1

    subgraph Requirements["Requirements Gathering"]
        R1["Collect Technical
Requirements"]
        R2["Review Current
Infrastructure"]
        R3["Define Integration
Points"]
    end

    R1 --> R2
    R2 --> R3
    R3 --> REVIEW

    subgraph Review["Coordination Review"]
        REVIEW["Technical Review
with Client"]
        APPROVE{Approved?}
    end

    REVIEW --> APPROVE
    APPROVE -->|Yes| SPEC["Create Specification
Document"]
    APPROVE -->|No| REVISE["Revise Requirements"]

    REVISE --> R1

    SPEC --> IMPL["Implementation
Phase"]
    IMPL --> VALIDATE["Validation
Phase"]
    VALIDATE --> HANDOVER["Production
Handover"]

    style Requirements fill:#e3f2fd,stroke:#1565c0,stroke-width:2px
    style Review fill:#fff3e0,stroke:#ef6c00,stroke-width:2px
    style IMPL fill:#e8f5e9,stroke:#2e7d32,stroke-width:2px
    style HANDOVER fill:#fce4ec,stroke:#c2185b,stroke-width:2px